Particular embodiments generally relate to power packages.
With the continual development of the electronics industry, an increasing number of devices are being integrated on printed circuit boards (PCB), and therefore the miniaturization of devices has become an inevitable trend in the development of device encapsulation technology. Single devices that occupy smaller areas enable the PCB to accommodate more devices per unit area, thereby providing greater room for compromise between miniaturization and high performance for the board designer.
With the rapid upgrade of electrical production, small, thin, and lightweight packages are a trend for electrical devices. In a dual-power application, multiple metal oxide semiconductor field effect transistor (MOSFET) devices may be included. A CMOS circuit is the most common unit on a PCB. CMOS circuits often require several NMOS and PMOS, for example a CMOS inverter requires at least one NMOS and one PMOS. Early single supply SO8 packages occupied an area of 5 mm×6 mm on the PCB. However, owing to being single tube encapsulation, two packages are required to realize one basic CMOS unit. This may use more printed circuit board (PCB) area due to using two packages.
These have been superseded by the dual-power PAK SO8 packages. Although the monomer in the package simultaneously encloses two MOSFETs, the two grid leads at the high side and the low side must intersect on the PCB because of the package structure. Therefore a PCB with at least two layers is required, thereby increasing the application cost and hampering more wide-reaching applications. However, this design is not optimized for a layout with a pulse width modulation (PWM) controller. To connect both high side and low side gate pins to PWM controllers, a trace overlap needs to occur in the PCB design. The PCB design thus has multiple layers and a one-layer PCB design is not geometrically possible. This increases the cost of the package.